36.8.3 SLCDC Frame Rate Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register and the bit DFFRZS is cleared in the Status register.
| Name: | SLCDC_FRR |
| Offset: | 0x8 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DIV[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRESC[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 10:8 – DIV[2:0] Clock Division
Processed at beginning of next frame.
| Value | Name | Description |
|---|---|---|
| 0 | PRESC_CLK_DIV1 | Clock output from prescaler is divided by 1 |
| 1 | PRESC_CLK_DIV2 | Clock output from prescaler is divided by 2 |
| 2 | PRESC_CLK_DIV3 | Clock output from prescaler is divided by 3 |
| 3 | PRESC_CLK_DIV4 | Clock output from prescaler is divided by 4 |
| 4 | PRESC_CLK_DIV5 | Clock output from prescaler is divided by 5 |
| 5 | PRESC_CLK_DIV6 | Clock output from prescaler is divided by 6 |
| 6 | PRESC_CLK_DIV7 | Clock output from prescaler is divided by 7 |
| 7 | PRESC_CLK_DIV8 | Clock output from prescaler is divided by 8 |
Bits 2:0 – PRESC[2:0] Clock Prescaler
Processed at beginning of next frame.
| Value | Name | Description |
|---|---|---|
| 0 | SLCK_DIV8 | Slow clock is divided by 8 |
| 1 | SLCK_DIV16 | Slow clock is divided by 16 |
| 2 | SLCK_DIV32 | Slow clock is divided by 32 |
| 3 | SLCK_DIV64 | Slow clock is divided by 64 |
| 4 | SLCK_DIV128 | Slow clock is divided by 128 |
| 5 | SLCK_DIV256 | Slow clock is divided by 256 |
| 6 | SLCK_DIV512 | Slow clock is divided by 512 |
| 7 | SLCK_DIV1024 | Slow clock is divided by 1024 |