36.8.1 SLCDC Control Register
This register can only be written if the WPCREN bit is cleared in the SLCDC Write Protection Mode Register.
| Name: | SLCDC_CR |
| Offset: | 0x0 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRZKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FRZMAP | FRZDF | SWRST | LCDDIS | LCDEN | |||||
| Access | W | W | W | W | W | ||||
| Reset | – | – | – | – | – |
Bits 15:8 – FRZKEY[7:0] Freeze Key
| Value | Name | Description |
|---|---|---|
| 0x4E | PASSWD |
Writing any other value in this field aborts the write operation of the FRZDF bit or FRZMAP bit. Always reads as 0. |
Bit 7 – FRZMAP Freeze Remap Configuration
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Freezes the configuration of remap registers until a VDDLCD power-up is performed (the SLCDC_CR.SWRST has no effect) if FRZKEY corresponds to 0x4E). |
Bit 6 – FRZDF Freeze Display Features Configuration
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Freezes the configuration of SLCDC_MR and SLCDC_FRR until a VDDLCD power-up is performed (the SLCDC_CR.SWRST has no effect) if FRZKEY corresponds to 0x4E. For example, the configuration of a number of commons/segments is protected against any software error. The FRZKEY must be written to 0x4E at the same time to enable the freeze of remap registers. |
Bit 3 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Equivalent to a power-up reset. When this command is performed, the SLCDC immediately ties all segments end commons lines to values corresponding to a “ground voltage”. |
Bit 1 – LCDDIS Disable LCDC
LCDDIS is processed at the beginning of the next frame.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The SLCDC is disabled. |
Bit 0 – LCDEN Enable the LCDC
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | The SLCDC is enabled. |