36.8.6 SLCDC Interrupt Enable Register
This register can only be written if the WPITEN bit is cleared in the SLCDC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | SLCDC_IER |
| Offset: | 0x20 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIS | ENDFRAME | ||||||||
| Access | W | W | |||||||
| Reset | – | – |