36.8.7 SLCDC Interrupt Disable Register

This register can only be written if the WPITEN bit is cleared in the SLCDC Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name: SLCDC_IDR
Offset: 0x24
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      DIS ENDFRAME 
Access WW 
Reset –– 

Bit 2 – DIS Disable Completion Interrupt Disable

Bit 0 – ENDFRAME End of Frame Interrupt Disable