47.8.17 MCSPI Two-Pin Mode Register
This register can only be written if the WPEN bit is cleared in the MCSPI Write Protection Mode Register.
| Name: | MCSPI_TPMR |
| Offset: | 0x50 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSR[1:0] | MIL | CSM | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:2 – OSR[1:0] Oversampling Rate
Defines the MCP3910 OSR setting used.
Bit 1 – MIL Multiple Input Lines
| Value | Description |
|---|---|
| 0 | The MCSPI manages a single MOSI line (data multiplexing must be performed externally). When a single MCP3910 is driven, CSM and MIL must be written to 0. |
| 1 | The MCSPI manages up to four MOSI lines and data multiplexing is done internally. |
Bit 0 – CSM Chip Select Mode
| Value | Description |
|---|---|
| 0 |
Chip select is not driven. When a single MCP3910 is driven, CSM and MIL must be written to 0. |
| 1 |
Chip select is driven and can be used to control enable pin of external device. Depending of the MCSPI_MR.PCSDEC bit, an external decoder can be used to minimize the number of IOs used. |