47.8.2 MCSPI Mode Register


Bit	31	30	29	28	27	26	25	24
	DLYBCS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
					PCS[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MOSIIE	CSIE	TPMEN	CMPMODE			TMCSMUX	LSBHALF
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			0	0


Bit	7	6	5	4	3	2	1	0
	LLB	CRCEN	WDRBT	MODFDIS	BRSRCCLK	PCSDEC	PS	MSTR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – DLYBCS[7:0] Delay Between Chip Selects

This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time guarantees nonoverlapping chip selects and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is lower than 6, six peripheral clock periods are inserted by default.

Otherwise, the following equations determine the delay:

If BRSRCCLK = 0:

Delay Between Chip Selects = \frac{DLYBCS}{f_{peripheral clock}}

If BRSRCCLK = 1:

Delay Between Chip Selects = \frac{DLYBCS}{f_{GCLK}}

Bits 19:16 – PCS[3:0] Peripheral Chip Select

This field is only used if fixed peripheral select is active (PS = 0).

If MCSPI_MR.PCSDEC = 0:

PCS = xxx0 NPCS[3:0] = 1110

PCS = xx01 NPCS[3:0] = 1101

PCS = x011 NPCS[3:0] = 1011

PCS = 0111 NPCS[3:0] = 0111

PCS = 1111 forbidden (no peripheral is selected)

(x = don’t care)

If MCSPI_MR.PCSDEC = 1:

NPCS[3:0] output signals = PCS.

Bit 15 – MOSIIE MOSI Inversion Enable

Value	Description
0	MOSI inputs are used “as is” by the IP.
1	MOSI inputs are internally inverted before being used by the IP.

Bit 14 – CSIE Chip Select Inversion Enable

Value	Description
0	Chip select NPCS IOs use the MCSPI standard “active low” scheme.
1	Chip select NPCS IOs use an “active high” scheme

Bit 13 – TPMEN Two-Pin Mode Enable

Value	Description
0	Two-Wire mode is disabled.
1	Two-Wire mode is enabled.

Bit 12 – CMPMODE Comparison Mode

Value	Name	Description
0	FLAG_ONLY	Any character is received and comparison function drives CMP flag.
1	START_CONDITION	Comparison condition must be met to start reception of all incoming characters until REQCLR is set.

Bit 9 – TMCSMUX Two-pin MOSI Chip Select External Multiplexing Mode

Value	Name	Description
0	DISABLED	Multiplexing of external MOSI lines is not required via Chip Select lines. When MCSPI_MR.TPMEN=0, MCSPI_TWMR.MIL=1 or MCSPI_TWMR.CSM=0, TMCSMUX must be written to 0.
1	ENABLED	Enables external multiplexing of MOSI lines via Chip Select lines. When MCSPI_MR.TPMEN=1, TMCSMUX must be written to 1 if MCSPI_TWMR.MIL=0 and MCSPI_TWMR.CSM=1.

Bit 8 – LSBHALF LSB Timing Selection

Value	Description
0	To be used only if SPI client LSB timing is 100% compliant with SPI standard (LSB duration is a full bit time). This value provides the best margin for SPI client response delay (less than 1 SPCK clock cycle).
1	To be selected if the SPI client LSB timing does not behave as the SPI standard (not triggered by NPCS deassertion in mode); the client response delay is limited to less than 1/2 SPCK cycle.

Bit 7 – LLB Local Loopback Enable

LLB controls the local loopback on the data shift register for testing in Host mode only (MISO is internally connected on MOSI).

Value	Description
0	Local loopback path disabled.
1	Local loopback path enabled.

Bit 6 – CRCEN CRC Enable

Value	Description
0	CRC calculation is disabled.
1	CRC calculation is enabled. The BITS field in MCSPI_CSRx registers must be at value ‘0’.

Bit 5 – WDRBT Wait for Data Read Before Transfer

Value	Description
0	No Effect. In Host mode, a transfer can be initiated regardless of MCSPI_RDR state.
1	In Host mode, a transfer can start only if MCSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.

Bit 4 – MODFDIS Mode Fault Detection

Value	Description
0	Mode fault detection enabled
1	Mode fault detection disabled

Bit 3 – BRSRCCLK Bit Rate Source Clock

0 (PERIPH_CLK): The peripheral clock is the source clock for the bit rate generation.

1 (GCLK): PMC GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.

Note: If bit BRSRCCLK = 1, the MCSPI_CSRx.SCBR field must be programmed with a value greater than 1.

Bit 2 – PCSDEC Chip Select Decode

When PCSDEC = 1, up to 15 chip select signals can be generated with the four NPCS lines using an external 4-bit to 16-bit decoder. The chip select registers define the characteristics of the 15 chip selects, with the following rules:

MCSPI_CSR0 defines peripheral chip select signals 0 to 3.

MCSPI_CSR1 defines peripheral chip select signals 4 to 7.

MCSPI_CSR2 defines peripheral chip select signals 8 to 11.

MCSPI_CSR3 defines peripheral chip select signals 12 to 14.

Value	Description
0	The chip select lines are directly connected to a peripheral device.
1	The four NPCS chip select lines are connected to a 4-bit to 16-bit decoder.

Bit 1 – PS Peripheral Select

Value	Description
0	Fixed Peripheral Select
1	Variable Peripheral Select

Bit 0 – MSTR Host/Client Mode

Value	Description
0	MCSPI is in Client mode.
1	MCSPI is in Host mode.

Name:	MCSPI_MR
Offset:	0x04
Reset:	0x00000000
Property:	Read/Write