47.8.10 MCSPI Interrupt Disable Register

This register can only be written if the WPITEN bit is cleared in the MCSPI Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name: MCSPI_IDR
Offset: 0x18
Reset: –
Property: Write-only

Bit 3130292827262524 
 RXFPTEFTXFPTEFRXFTHFRXFFFRXFEFTXFTHFTXFFFTXFEF 
Access WWWWWWWW 
Reset –––––––– 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   CRCERR CMPUNDESTXEMPTYNSSR 
Access WWWWW 
Reset ––––– 
Bit 76543210 
 TXBUFERXBUFFENDTXENDRXOVRESMODFTDRERDRF 
Access WWWWWWWW 
Reset –––––––– 

Bit 31 – RXFPTEF RXFPTEF Interrupt Disable

Bit 30 – TXFPTEF TXFPTEF Interrupt Disable

Bit 29 – RXFTHF RXFTHF Interrupt Disable

Bit 28 – RXFFF RXFFF Interrupt Disable

Bit 27 – RXFEF RXFEF Interrupt Disable

Bit 26 – TXFTHF TXFTHF Interrupt Disable

Bit 25 – TXFFF TXFFF Interrupt Disable

Bit 24 – TXFEF TXFEF Interrupt Disable

Bit 13 – CRCERR CRC Error Interrupt Disable

Bit 11 – CMP Comparison Interrupt Disable

Bit 10 – UNDES Underrun Error Interrupt Disable

Bit 9 – TXEMPTY Transmission Registers Empty Disable

Bit 8 – NSSR NSS Rising Interrupt Disable

Bit 7 – TXBUFE Transmit Buffer Empty Interrupt Disable

Bit 6 – RXBUFF Receive Buffer Full Interrupt Disable

Bit 5 – ENDTX End of Transmit Buffer Interrupt Disable

Bit 4 – ENDRX End of Receive Buffer Interrupt Disable

Bit 3 – OVRES Overrun Error Interrupt Disable

Bit 2 – MODF Mode Fault Error Interrupt Disable

Bit 1 – TDRE MCSPI Transmit Data Register Empty Interrupt Disable

Bit 0 – RDRF Receive Data Register Full Interrupt Disable