47.8.8 MCSPI Status Register


Bit	31	30	29	28	27	26	25	24
	RXFPTEF	TXFPTEF	RXFTHF	RXFFF	RXFEF	TXFTHF	TXFFF	TXFEF
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
								SPIENS
Access								R
Reset								0


Bit	15	14	13	12	11	10	9	8
			CRCERR	SFERR	CMP	UNDES	TXEMPTY	NSSR
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TXBUFE	RXBUFF	ENDTX	ENDRX	OVRES	MODF	TDRE	RDRF
Access	R	R	R	R	R	R	R	R
Reset	1	1	1	1	0	0	0	0

Bit 31 – RXFPTEF Receive FIFO Pointer Error Flag

See FIFO Pointer Error for details.

Value	Description
0	No Receive FIFO pointer occurred
1	Receive FIFO pointer error occurred. Receiver must be reset.

Bit 30 – TXFPTEF Transmit FIFO Pointer Error Flag

See FIFO Pointer Error for details.

Value	Description
0	No Transmit FIFO pointer occurred
1	Transmit FIFO pointer error occurred. Transceiver must be reset

Bit 29 – RXFTHF Receive FIFO Threshold Flag

Value	Description
0	Number of unread data in Receive FIFO is below RXFTHRES threshold or RXFTH flag has been cleared.
1	Number of unread data in Receive FIFO has reached RXFTHRES threshold (coming from “below threshold” state to “equal or above threshold” state).

Bit 28 – RXFFF Receive FIFO Full Flag

Value	Description
0	Receive FIFO is not empty or RXFE flag has been cleared.
1	Receive FIFO has become full (coming from “not full” state to “full” state).

Bit 27 – RXFEF Receive FIFO Empty Flag

Value	Description
0	Receive FIFO is not empty or RXFE flag has been cleared.
1	Receive FIFO has become empty (coming from “not empty” state to “empty” state).

Bit 26 – TXFTHF Transmit FIFO Threshold Flag (cleared on read)

Value	Description
0	Number of data in Transmit FIFO is above TXFTHRES threshold.
1	Number of data in Transmit FIFO has reached TXFTHRES threshold since the last read of MCSPI_SR.

Bit 25 – TXFFF Transmit FIFO Full Flag (cleared on read)

Value	Description
0	Transmit FIFO is not full or TXFF flag has been cleared.
1	Transmit FIFO has been filled since the last read of MCSPI_SR.

Bit 24 – TXFEF Transmit FIFO Empty Flag (cleared on read)

Value	Description
0	Transmit FIFO is not empty.
1	Transmit FIFO has been emptied since the last read of MCSPI_SR.

Bit 16 – SPIENS MCSPI Enable Status

Value	Description
0	MCSPI is disabled.
1	MCSPI is enabled.

Bit 13 – CRCERR CRC Error (cleared on read)

Value	Description
0	CRC calculation is disabled or no received frame contains CRC error since the last read of MCSPI_SR.
1	Since the last read of MCSPI_SR, a received frame contains a CRC error.

Bit 12 – SFERR Client Frame Error (cleared on read)

Value	Description
0	There is no frame error detected for a client access since the last read of MCSPI_SR.
1	In Client mode, the chip select raised while the transfer of the character defined in MCSPI_CSR0.BITS was not complete.

Bit 11 – CMP Comparison Status (cleared on read)

Value	Description
0	No received character matched the comparison criteria programmed in the VAL1 and VAL2 fields in MCSPI_CMPR since the last read of MCSPI_SR.
1	A received character matched the comparison criteria since the last read of MCSPI_SR.

Bit 10 – UNDES Underrun Error Status (Client mode only) (cleared on read)

Value	Description
0	No underrun has been detected since the last read of MCSPI_SR.
1	A transfer starts whereas no data has been loaded in MCSPI_TDR.

Bit 9 – TXEMPTY Transmission Registers Empty (cleared by writing MCSPI_TDR)

Value	Description
0	As soon as data is written in MCSPI_TDR.
1	MCSPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set after the end of this delay.

Bit 8 – NSSR NSS Rising (cleared on read)

Value	Description
0	No rising edge detected on NSS pin since the last read of MCSPI_SR.
1	A rising edge occurred on NSS pin since the last read of MCSPI_SR.

Bit 7 – TXBUFE TX Buffer Empty (cleared by writing MCSPI_TCR or MCSPI_TNCR)

Note: MCSPI_TCR and MCSPI_TNCR are PDC registers.

Value	Description
0	MCSPI_TCR or MCSPI_TNCR has a value other than 0.
1	Both MCSPI_TCR and MCSPI_TNCR have a value of 0.

Bit 6 – RXBUFF RX Buffer Full (cleared by writing MCSPI_RCR or MCSPI_RNCR)

Note: MCSPI_RCR and MCSPI_RNCR are PDC registers.

Value	Description
0	MCSPI_RCR or MCSPI_RNCR has a value other than 0.
1	Both MCSPI_RCR and MCSPI_RNCR have a value of 0.

Bit 5 – ENDTX End of TX Buffer (cleared by writing MCSPI_TCR or MCSPI_TNCR)

Note: MCSPI_TCR and MCSPI_TNCR are PDC registers.

Value	Description
0	The Transmit Counter register has not reached 0 since the last write in MCSPI_TCR or MCSPI_TNCR.
1	The Transmit Counter register has reached 0 since the last write in MCSPI_TCR or MCSPI_TNCR.

Bit 4 – ENDRX End of RX Buffer (cleared by writing MCSPI_RCR or MCSPI_RNCR)

Note: MCSPI_RCR and MCSPI_RNCR are PDC registers.

Value	Description
0	The Receive Counter register has not reached 0 since the last write in MCSPI_RCR or MCSPI_RNCR.
1	The Receive Counter register has reached 0 since the last write in MCSPI_RCR or MCSPI_RNCR.

Bit 3 – OVRES Overrun Error Status (cleared on read)

An overrun occurs when MCSPI_RDR is loaded at least twice from the internal shift register since the last read of MCSPI_RDR.

Value	Description
0	No overrun has been detected since the last read of MCSPI_SR.
1	An overrun has occurred since the last read of MCSPI_SR.

Bit 2 – MODF Mode Fault Error (cleared on read)

Value	Description
0	No mode fault has been detected since the last read of MCSPI_SR.
1	A mode fault occurred since the last read of MCSPI_SR.

Bit 1 – TDRE Transmit Data Register Empty (cleared by writing MCSPI_TDR)

When FIFOs are disabled:

0: Data has been written to MCSPI_TDR and not yet transferred to the internal shift register.

1: The last data written in MCSPI_TDR has been transferred to the internal shift register.

TDRE is cleared when the MCSPI is disabled or at reset. Enabling the MCSPI sets the TDRE flag.

When FIFOs are enabled:

0: Transmit FIFO is full and cannot accept more data.

1: Transmit FIFO is not full; one or more data can be written according to TXRDYM field configuration.

TDRE behavior with FIFO enabled is illustrated in TXEMPTY, TDRE and RDRF Behavior.

Bit 0 – RDRF Receive Data Register Full (cleared by reading MCSPI_RDR)

When FIFOs are disabled:

0: No data has been received since the last read of MCSPI_RDR.

1: Data has been received and the received data has been transferred from the internal shift register to MCSPI_RDR since the last read of MCSPI_RDR.

When FIFOs are enabled:

0: Receive FIFO is empty; no data to read.

1: At least one unread data is in the Receive FIFO.

RDRF behavior with FIFO enabled is illustrated in TXEMPTY, TDRE and RDRF Behavior.

Name:	MCSPI_SR
Offset:	0x10
Reset:	0x000000F0
Property:	Read-only