47.8.1 MCSPI Control Register

This register can only be written if the WPCREN bit is cleared in the MCSPI Write Protection Mode Register.

Name:	MCSPI_CR
Offset:	0x00
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24
	FIFODIS	FIFOEN						LASTXFER
Access	W	W						W
Reset	–	–						–


Bit	23	22	21	20	19	18	17	16
							RXFCLR	TXFCLR
Access							W	W
Reset							–	–


Bit	15	14	13	12	11	10	9	8
				REQCLR
Access				W
Reset				–


Bit	7	6	5	4	3	2	1	0
	SWRST						SPIDIS	SPIEN
Access	W						W	W
Reset	–						–	–

Bit 31 – FIFODIS FIFO Disable

Value	Description
0	No effect.
1	Disables the Transmit and Receive FIFOs.

Bit 30 – FIFOEN FIFO Enable

Value	Description
0	No effect.
1	Enables the Transmit and Receive FIFOs.

Bit 24 – LASTXFER Last Transfer

See Peripheral Selection for more details.

Value	Description
0	No effect.
1	The current NPCS is deasserted after the character written in TD has been transferred. When MCSPI_CSRx.CSAAT is set, the communication with the current serial peripheral can be closed by raising the corresponding NPCS line as soon as TD transfer is completed.

Bit 17 – RXFCLR Receive FIFO Clear

Value	Description
0	No effect.
1	Empties the Receive FIFO.

Bit 16 – TXFCLR Transmit FIFO Clear

Value	Description
0	No effect.
1	Empties the Transmit FIFO.

Bit 12 – REQCLR Request to Clear the Comparison Trigger


Value	Description
`0`	No effect.
`1`	Restarts the comparison trigger to enable MCSPI_RDR loading.

Bit 7 – SWRST MCSPI Software Reset

The MCSPI is in Client mode after software reset.

PDC channels are not affected by software reset.

Value	Description
0	No effect.
1	Resets the MCSPI. A software-triggered hardware reset of the MCSPI interface is performed.

Bit 1 – SPIDIS MCSPI Disable

All pins are set in Input mode after completion of the transmission in progress, if any.

If a transfer is in progress when SPIDIS is set, the MCSPI completes the transmission of the shifter register and does not start any new transfer, even if MCSPI_THR is loaded.

Note: If both SPIEN and SPIDIS are equal to one when MCSPI_CR is written, the MCSPI is disabled.

Value	Description
0	No effect.
1	Disables the MCSPI.

Bit 0 – SPIEN MCSPI Enable

Value	Description
0	No effect.
1	Enables the MCSPI to transfer and receive data.