47.7.3.6 Peripheral Deselection without PDC

During a transfer of more than one unit of data on a chip select without the PDC, MCSPI_TDR is loaded by the processor, the TDRE flag rises as soon as the content of MCSPI_TDR is transferred into the internal shift register. When this flag is detected high, MCSPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the chip select is not deasserted between the two transfers. But depending on the application software handling the MCSPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor may not reload MCSPI_TDR in time to keep the chip select active (low). A null DLYBCT value (delay between consecutive transfers) in MCSPI_CSR, gives even less time for the processor to reload MCSPI_TDR. With some MCSPI client peripherals, if the chip select line must remain active (low) during a full set of transfers, communication errors can occur.

To facilitate interfacing with such devices, the chip select registers [MCSPI_CSR0...MCSPI_CSR3] can be programmed with the MCSPI_CSRx.CSAAT bit at 1. This allows the chip select lines to remain in their current state (low = active) until a transfer to another chip select is required. Even if MCSPI_TDR is not reloaded, the chip select remains active. To deassert the chip select line at the end of the transfer, the MCSPI_SR.LASTXFER bit must be set after writing the last data to transmit into MCSPI_TDR.