47.7.3.1 Clock Generation

The MCSPI baud rate clock is generated by dividing the peripheral clock by a value between 1 and 255.

If the Serial Clock Bit Rate (SCBR) field in MCSPI_CSRx is programmed to 1, the operating baud rate is peripheral clock (refer to the section “Electrical Characteristics” for the SPCK maximum frequency). Triggering a transfer while SCBR is at 0 can lead to unpredictable results.

At reset, SCBR=0 and the user has to program it to a valid value before performing the first transfer.

The divisor can be defined independently for each chip select, as it has to be programmed in SCBR. This allows the MCSPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.

If GCLK is selected as the source clock (MCSPI_MR.BRSRCCLK = 1), the bit rate is independent of the processor/bus clock and MCSPI_CSRx.SCBR must set to 2 or higher. Thus, the processor clock can be changed while the MCSPI is enabled. The processor clock frequency changes must be performed only by programming PMC_MCKR.PRES (refer to the section “Power Management Controller” (PMC)). Any other method to modify the processor/bus clock frequency (PLL multiplier, etc.) is forbidden when the MCSPI is enabled.

The peripheral clock frequency must be at least three times higher than GCLK frequency. SPCK clock jitter is minimized when the ratio between peripheral clock and GCLK is the greatest.