1.3.2 Design Implementation

The following figure shows the top-level Libero implementation of the demo design.

Figure 1-2. Top-Level Libero® Implementation

The following table lists the important I/O signals of the design.

Table 1-2. I/O Signals
SignalDirectionDescription
RX_P, RX_NInputIOD CDR receive signals connected to the VSC PHY transmit data signals
TX_P, TX_NOutputIOD CDR transmit signals connected to the VSC PHY receive data signals
REFCLK_N, REFCLK_PInputReceives 125 MHz input clock from the on-board ZL30364 and feeds to NWC_PLL_0
RESET_NInputActive low Mi-V reset

Asserted by pressing the on-board K22 push-button.

REF_CLK_0InputReceives 50 MHz input clock from the on-board 50 MHz oscillator and feeds to PF_CCC_0
TCK, TDI, TMS, TRSTBInputJTAG signals interface to the soft processor for debugging
LINK_OKOutputLink status indicator

Provides the link up or down status with the on-board PHY. This signal is mapped to on-board LED7.

The LED ON state indicates that the link is up.

PHY_RSTOutputActive high reset signal to the on-board VSC8575 PHY
PHY_MDCOutputManagement Data IO clock is fed to the on-board VSC8575 PHY
PHY_MDIOOutputManagement Data IO Interface for accessing the on-board VSC8575 PHY registers
coma_modeOutputSignal is held low to keep the VSC PHY fully active when it is out of reset
REF_CLK_SELOutputReference clock speed pin of the VSC PHY.

Held high for selecting the 125 MHz reference clock speed.

RD_BC_ERROROutputCoreTSE receive error signal

This LED signal indicates the receive code group error. This signal is synchronous to RX_CLK_R, and it is mapped to LED4 on the board.

When the LED is in ON state, there is an error in the received code group.

When the LED is in OFF state, there is no error.

SPISCLKO, SPISS, SPISDO, SPISDIOutputSerial Peripheral Interface (SPI) controller signals to interface with the ZL30364 clock generation hardware
TDOOutputJTAG test data output

Serial data output from tap.