1.3.1 About PF_IOD_CDR
(Ask a Question)The PF_IOD_CDR IP core provides an asynchronous receive and transmit interface that supports up to 1.6 Gbps speed for serial data transfers. It supports the SGMII interface. PF_IOD_CDR uses the DDRX5 IO Gearing mode for the SGMII interface with a 10:1 digital ratio to provide 10-bit data width for both transmit and receive. The clock recovery circuit, which is part of this PF_IOD_CDR, keeps the receive clock centered in the data eye.
The PF_IOD_CDR interface is compatible with the CoreTSE, the CoreTSE_AHB, and the CoreSGMII IP cores configured in TBI mode. In this demo, the CoreTSE (Non-AMBA) MAC is used in the TBI mode to transmit and receive the Ethernet packets.