54.15 USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001782 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000724 - Embedded Hosts > Full Speed
Electrical configuration required to be USB-compliant:
- the CPU frequency must be higher than 16 MHz when USB is active (No constraint for USB suspend mode)
- the operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- the GCLK_USB frequency accuracy
source must be less than:
- in USB FS device mode, 48MHz +/-0.25%
- in USB FS host mode, 48MHz +/-0.05%
| Clock setup | USB Device | USB Host | |
|---|---|---|---|
| DFLL48M | Open loop | No | No |
| Close loop, Ref. internal RC OSC source | No | No | |
| Close loop, Ref. external XOSC source | Yes | No | |
| Close loop, Ref. SOF (USB recovery mode)(1) | Yes(2) | N/A | |
| FDPLL | internal RC OSC (32K, 8M…) | No | No |
| external OSC (<1MHz) | Yes | No | |
| external OSC (>1MHz) | Yes(3) | Yes | |
Note:
- When using DFLL48M in USB recovery mode, the Fine Step value must be 0xA to guarantee a USB clock at +/-0.25% before 11ms after a resume. Only usable in LDO regulator mode.
- Very high signal quality and crystal-less. It is the best setup for USB Device mode.
- FDPLL lock time is short when the clock frequency source is high (> 1 MHz). Thus, FDPLL and external OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up time (See TDRSMDN in the USB 2.0 specification).