54.12 NVM Characteristics

Table 54-38. NVM Flash Read Wait States for Worst Case Conditions (EFP part numbers)
Wait States (WS)	0 WS	1 WS	2 WS	3 WS	4 WS	5 WS	6 WS	Auto WS
Read Operations	1 Cycle	2 Cycles	3 Cycles	4 Cycles	5 Cycles	6 Cycles	7 Cycles	n Cycles
CPU FMax (MHz)⁽¹⁾	19	38	57	76	95	100	120	120

Note:

VDD > 1.71V.

Table 54-39. NVM Flash Read Wait States for Worst Case Conditions (non-EFP part numbers)
Wait States (WS)	0 WS	1 WS	2 WS	3 WS	4 WS	5 WS	Auto WS
Read Operations	1 Cycle	2 Cycles	3 Cycles	4 Cycles	5 Cycles	6 Cycles	N Cycles
CPU FMax (MHz)⁽¹⁾	24	51	77	101	119	120	120
CPU FMax (MHz)⁽²⁾	22	44	67	89	111	120	120

Note:

VDD > 2.7V.
1.71V < VDD <= 2.7V.

Maximum operating frequencies are given in the table above in MHz, but are limited by the Embedded Flash access time when the processor is fetching code out of it. Theses tables provide the device maximum operating frequency defined by the field RWS of the NVMCTRL CTRLA register when automatic wait states (AUTOWS) is disabled. This field defines the number of Wait states required to access the Embedded Flash Memory.

Table 54-40. Flash Timing Characteristics
Symbol	Parameter	Conditions	Typ.	Max.	Units
t_FPW	Program Cycle Time	Write Page	1.5	3⁽¹⁾	ms
t_CE		Chip Erase	6.4	25 ⁽¹⁾	s
t_FEB		Erase Block	50	200 ⁽¹⁾	ms

Note:

These are based on simulation. They are not covered by production test limits or characterization.

Table 54-41. Flash Endurance and Data Retention
Symbol	Parameter	Conditions	Min.	Typ.	Units
Ret_NVM10k	Retention after up to 10k	At TA = 85°C	20	-	Years
Cyc_NVM	Cycling Endurance⁽¹⁾	At TA = 85°C	10K	-	Cycles

Note:

An endurance cycle is a write-and-erase operation.

Table 54-42. Flash Erase and Programming Current
Symbol	Parameter	Typ.	Max.	Units
I_FAP	Active Current current during whole programming operation	8		mA
I_FAE	Active Current current during Erase operation	8		mA