12.10.4 PIE2

Peripheral Interrupt Enable Register 2
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1 through PIE4.
Name: PIE2
Offset: 0x0098

Bit 76543210 
 CLC2IECLC1IECWG1IENCO1IECCP2IECCP1IETMR6IETMR4IE 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – CLC2IE  CLC2 Interrupt Enable

ValueDescription
1 CLC2 interrupts are enabled
0 CLC2 interrupts are disabled

Bit 6 – CLC1IE CLC1 Interrupt Enable

ValueDescription
1 CLC1 interrupts are enabled
0 CLC1 interrupts are disabled

Bit 5 – CWG1IE CWG1 Interrupt Enable

ValueDescription
1 CWG1 interrupts are enabled
0 CWG1 interrupts are disabled

Bit 4 – NCO1IE NCO1 Interrupt Enable

ValueDescription
1 NCO1 interrupts are enabled
0 NCO1 interrupts are disabled

Bit 3 – CCP2IE CCP2 Interrupt Enable

ValueDescription
1 CCP2 interrupts are enabled
0 CCP2 interrupts are disabled

Bit 2 – CCP1IE CCP1 Interrupt Enable

ValueDescription
1 CCP1 interrupts are enabled
0 CCP1 interrupts are disabled

Bit 1 – TMR6IE TMR6 Interrupt Enable

ValueDescription
1 TMR6 interrupts are enabled
0 TMR6 interrupts are disabled

Bit 0 – TMR4IE TMR4 Interrupt Enable

ValueDescription
1 TMR4 interrupts are enabled
0 TMR4 interrupts are disabled
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1 through PIE4.