12.10.7 PIR0
Note:
- The External Interrupt INT pin is selected by INTPPS.
- The IOCIF bit is the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag, application firmware must clear all of the lower level IOCAF-IOCEF register bits.
- Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: | PIR0 |
Offset: | 0x008C |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TMR0IF | IOCIF | INTF | |||||||
Access | R/W/HS | R | R/W/HS | ||||||
Reset | 0 | 0 | 0 |
Bit 5 – TMR0IF Timer0 Interrupt Flag
Value | Description |
---|---|
1 | TMR0 register has overflowed (must be cleared by software) |
0 | TMR0 register has not overflowed |
Bit 4 – IOCIF Interrupt-on-Change Flag(2)
Value | Description |
---|---|
1 | One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge was detected by the IOC module |
0 | None of the IOCAF-IOCEF register bits are currently set |
Bit 0 – INTF External Interrupt Flag(1)
Value | Description |
---|---|
1 | External Interrupt has occurred |
0 | External Interrupt has not occurred |