12.10.11 PIR4

Peripheral Interrupt Request Register 4
Note:
  1. Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR4
Offset: 0x0090

Bit 76543210 
   ZCDIFADTIFADIFCM1IFBCL2IFSSP2IF 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 000000 

Bit 5 – ZCDIF Zero-Cross Detect (ZCD) Interrupt Flag

ValueDescription
1 A ZCD interrupt occurred (must be cleared in software)
0 A ZCD interrupt has not occurred

Bit 4 – ADTIF ADC Threshold Interrupt Flag

ValueDescription
1 ADC Threshold interrupt has occurred (must be cleared in software)
0 ADC Threshold interrupt event has not occurred

Bit 3 – ADIF ADC Interrupt Flag

ValueDescription
1 ADC interrupt has occurred (must be cleared in software)
0 ADC interrupt event has not occurred

Bit 2 – CM1IF Comparator 1 Interrupt Flag

ValueDescription
1 Comparator 1 interrupt has occurred (must be cleared in software)
0 Comparator 1 interrupt event has not occurred

Bit 1 – BCL2IF MSSP2 Bus Collision Interrupt Flag

ValueDescription
1 An MSSP2 Bus Collision interrupt has occurred (must be cleared in software)
0 No MSSP2 Bus Collision event was detected

Bit 0 – SSP2IF MSSP2 Interrupt Flag

ValueDescription
1 MSSP 2 interrupt has occurred (must be cleared in software)
0 MSSP2 interrupt event has not occurred
Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.