12.10.9 PIR2

Peripheral Interrupt Request Register 2
Note: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR2
Offset: 0x008E

Bit 76543210 
 CLC2IFCLC1IFCWG1IFNCO1IFCCP2IFCCP1IFTMR6IFTMR4IF 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 00000000 

Bit 7 – CLC2IF CLC2 Interrupt Flag

ValueDescription
1CLC2 interrupt has occurred (must be cleared in software)
0CLC2 interrupt event has not occurred

Bit 6 – CLC1IF CLC1 Interrupt Flag

ValueDescription
1CLC1 interrupt has occurred (must be cleared in software)
0CLC1 interrupt event has not occurred

Bit 5 – CWG1IF CWG1 Interrupt Flag

ValueDescription
1CWG1 interrupt has occurred (must be cleared in software)
0CWG1 interrupt event has not occurred

Bit 4 – NCO1IF NCO1 Interrupt Flag

ValueDescription
1NCO1 interrupt has occurred (must be cleared in software)
0NCO1 interrupt event has not occurred

Bit 3 – CCP2IF CCP2 Interrupt Flag

ValueCCP Mode
CaptureComparePWM
1Capture occurred (must be cleared in software)Compare match occurred (must be cleared in software)Output trailing edge occurred (must be cleared in software)
0Capture did not occurCompare match did not occurOutput trailing edge did not occur

Bit 2 – CCP1IF CCP1 Interrupt Flag

ValueCCP Mode
CaptureComparePWM
1Capture occurred (must be cleared in software)Compare match occurred (must be cleared in software)Output trailing edge occurred (must be cleared in software)
0Capture did not occurCompare match did not occurOutput trailing edge did not occur

Bit 1 – TMR6IF TMR6 Interrupt Flag

ValueDescription
1TMR6 interrupt has occurred (must be cleared in software)
0TMR6 interrupt event has not occurred

Bit 0 – TMR4IF TMR4 Interrupt Flag

ValueDescription
1TMR4 interrupt has occurred (must be cleared in software)
0TMR4 interrupt event has not occurred
Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.