12.10.10 PIR3

Peripheral Interrupt Request Register 3
Note:
  1. RC2IF is read-only. User software must read RC2REG to clear RC2IF.
  2. TX2IF is read-only. User software must load TX2REG to clear TX2IF. TX2IF does not indicate a completed transmission (use TMRT for this purpose instead).
  3. RC1IF is read-only. User software must read RC1REG to clear RC1IF.
  4. TX1IF is read-only. User software must load TX1REG to clear TX1IF. TX1IF does not indicate a completed transmission (use TMRT for this purpose instead).
  5. Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.
Name: PIR3
Offset: 0x008F

Bit 76543210 
 BCL1IFSSP1IFRC2IFTX2IFRC1IFTX1IFCLC4IFCLC3IF 
Access R/W/HSR/W/HSRRRRR/W/HSR/W/HS 
Reset 00000000 

Bit 7 – BCL1IF MSSP1 Bus Collision Interrupt Flag

ValueDescription
1 An MSSP1 Bus Collision was detected (must be cleared in software)
0 No MSSP1 Bus Collision event was detected

Bit 6 – SSP1IF MSSP1 Interrupt Flag

ValueDescription
1 MSSP1 interrupt has occurred (must be cleared in software)
0 MSSP1 interrupt event has not occurred

Bit 5 – RC2IF  EUSART2 Receive Interrupt Flag(1)

ValueDescription
1 The EUSART2 receive buffer (RC2REG) is not empty (contains at least one byte)
0 The EUSART2 receive buffer is empty

Bit 4 – TX2IF  EUSART2 Transmit Interrupt Flag(2)

ValueDescription
1 The EUSART2 transmit buffer (TX2REG) is empty
0 The EUSART2 transmit buffer is not empty

Bit 3 – RC1IF  EUSART1 Receive Interrupt Flag(3)

ValueDescription
1 The EUSART1 receive buffer (RC1REG) is not empty (contains at least one byte)
0 The EUSART1 receive buffer is empty

Bit 2 – TX1IF  EUSART1 Transmit Interrupt Flag(4)

ValueDescription
1 The EUSART1 transmit buffer (TX1REG) is empty
0 The EUSART1 transmit buffer is not empty

Bit 1 – CLC4IF CLC4 Interrupt Flag

ValueDescription
1 CLC4 interrupt has occurred (must be cleared in software)
0 CLC4 interrupt event has not occurred

Bit 0 – CLC3IF CLC3 Interrupt Flag

ValueDescription
1 CLC3 interrupt has occurred (must be cleared in software)
0 CLC3 interrupt event has not occurred
RC2IF is read-only. User software must read RC2REG to clear RC2IF. TX2IF is read-only. User software must load TX2REG to clear TX2IF. TX2IF does not indicate a completed transmission (use TMRT for this purpose instead). RC1IF is read-only. User software must read RC1REG to clear RC1IF. TX1IF is read-only. User software must load TX1REG to clear TX1IF. TX1IF does not indicate a completed transmission (use TMRT for this purpose instead). Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable (GIE) bit. User software may ensure the appropriate interrupt flag bits are cleared before enabling an interrupt.