12.10.2 PIE0
Note:
- The External Interrupt INT pin is selected by INTPPS.
- Bit PEIE in the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1 through PIE4. Interrupt sources controlled by the PIE0 register do not require the PEIE bit to be set in order to allow interrupt vectoring (when the GIE bit in the INTCON register is set).
Name: | PIE0 |
Offset: | 0x0096 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TMR0IE | IOCIE | INTE | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit 5 – TMR0IE Timer0 Interrupt Enable
Value | Description |
---|---|
1 | TMR0 interrupts are enabled |
0 | TMR0 interrupts are disabled |
Bit 4 – IOCIE Interrupt-on-Change Enable
Value | Description |
---|---|
1 | IOC interrupts are enabled |
0 | IOC interrupts are disabled |
Bit 0 – INTE External Interrupt Enable(1)
Value | Description |
---|---|
1 | External interrupts are enabled |
0 | External interrupts are disabled |