6.2.1.1 LPDDR3 Routing Topology

The following figure shows the routing of the LPDDR3 address, control, DQ, and DM signals.

Figure 6-6. LPDDR3 Address/Control/DQ/DM Signal Routing

The following figure shows the routing of LPDDR3 clock and DQS signals.

Figure 6-7. LPDDR3 Clock and DQS signal Routing