6.2.1 LPDDR3 Layout Guidelines
(Ask a Question)The LPDDR3 is a point-to-point interface, where the data group signals and address/command signals are routed from point to point. As LPDDR3 is used in power sensitive designs, there is no termination used for point to point interface. PolarFire supports up to 1333 MT/s for LPDDR3 interface on HSIO only.
It is recommended to tightly length match the signals CK, ADDR/CMD signals in one group and DQS, DQ, DM signals in one group together to reduce the skew.
A characteristic impedance of 40-50Ω must be used for single-ended signals and 90-100Ω for differential signals.
Microchip recommends simulating the interface to tightly match the characteristic impedance of trace with driver impedance to reduce reflections and for any possible electrical and timing violations in meeting JEDEC requirements.
DQ bit swapping within a byte lane is supported on the PCB between the DDR controller and the LPDDR3 memory for routing flexibility.