5.3.1 QDR Controller

QDR Controller is a Soft IP Core that consists of the following blocks:

• Data Control: Accepts the Write and Read commands from User Interface and convert them to PHY commands. It controls the PHY to generate QDR memory interface signals such that, the memory device look into data with the correct latency-with respect to Address and Command (WPS_N and RPS_N).
• Training Logic: Controls PHY Delay Lines and De-skews (due to board and internal delays) Input data, Input Clocks, and Input Valid Signals.