2.5.2 DFI Interface

The DDR memory controller interface solution leverages the DDR PHY interface (DFI 4.0) for connections between the controller and the PHY. The control signal, write data, read data update, status, and training interfaces are listed in the following tables. Use the PolarFire FPGA DDR3/LPDDR3/DDR4 PHY configurator to expose the DFI interface. For more information about the interface, see the DFI 4.0 Specification available on the DFI Group DDR PHY website.

Table 2-16. DFI Control Signal Interface (synchronous to SYS_CLK)
Signal NameDirectionDescription
DFI_ADDRESS_P0InputDFI Address bus.
  • For DDR3, the width is [15:0].
  • For LPDDR3, the width is [19:0].
  • For DDR4, the width is [16:0].
DFI_ADDRESS_P1InputDFI Address bus.
  • For DDR3, the width is [15:0].
  • For LPDDR3, the width is [19:0].
  • For DDR4, the width is [16:0].
DFI_ADDRESS_P2InputDFI Address bus.
  • For DDR3, the width is [15:0].
  • For LPDDR3, the width is [19:0].
  • For DDR4, the width is [16:0].
DFI_ADDRESS_P3InputDFI Address bus.
  • For DDR3, the width is [15:0].
  • For LPDDR3, the width is [19:0].
  • For DDR4, the width is [16:0].
DFI_BANK_P0[2:0]InputDFI bank bus (only for DDR3 and DDR4).
DFI_BANK_P1[2:0]InputDFI bank bus (only for DDR3 and DDR4).
DFI_BANK_P2[2:0]InputDFI bank bus (only for DDR3 and DDR4).
DFI_BANK_P3[2:0]InputDFI bank bus (only for DDR3 and DDR4).
DFI_CAS_N_P0InputDFI column address strobe (only for DDR3 and DDR4).
DFI_CAS_N_P1InputDFI column address strobe (only for DDR3 and DDR4).
DFI_CAS_N_P2InputDFI column address strobe (only for DDR3 and DDR4).
DFI_CAS_N_P3InputDFI column address strobe (only for DDR3 and DDR4).
DFI_CKE_P0[0]InputDFI clock enable.
DFI_CKE_P1[0]InputDFI clock enable.
DFI_CKE_P2[0]InputDFI clock enable.
DFI_CKE_P3[0]InputDFI clock enable.
DFI_CS_N_P0[0]InputDFI chip select.
DFI_CS_N_P1[0]InputDFI chip select.
DFI_CS_N_P2[0]InputDFI chip select.
DFI_CS_N_P3[0]InputDFI chip select.
DFI_ODT_P0[0]InputDFI on-die termination control.
DFI_ODT_P1[0]InputDFI on-die termination control.
DFI_ODT_P2[0]InputDFI on-die termination control.
DFI_ODT_P3[0]InputDFI on-die termination control.
DFI_RAS_N_P0InputDFI row address strobe (only for DDR3 and DDR4).
DFI_RAS_N_P1InputDFI row address strobe (only for DDR3 and DDR4).
DFI_RAS_N_P2InputDFI row address strobe (only for DDR3 and DDR4).
DFI_RAS_N_P3InputDFI row address strobe (only for DDR3 and DDR4).
DFI_RESET_N_P0InputDFI reset.
DFI_RESET_N_P1InputDFI reset.
DFI_RESET_N_P2InputDFI reset.
DFI_RESET_N_P3InputDFI reset.
DFI_WE_N_P0InputDFI write enable (only for DDR3 and DDR4).
DFI_WE_N_P1InputDFI write enable (only for DDR3 and DDR4).
DFI_WE_N_P2InputDFI write enable (only for DDR3 and DDR4).
DFI_WE_N_P3InputDFI write enable (only for DDR3 and DDR4).
Table 2-17. DFI Write Data Interface
Signal NameDirectionDescription
DFI_WRDATA_CS_N_P0[0]InputDFI write data chip select
DFI_WRDATA_CS_N_P1[0]InputDFI write data chip select
DFI_WRDATA_CS_N_P2[0]InputDFI write data chip select
DFI_WRDATA_CS_N_P3[0]InputDFI write data chip select
DFI_WRDATA_EN_P0[63:0]1InputDFI write data and data mask enable
DFI_WRDATA_EN_P1[63:0]InputDFI write data and data mask enable
DFI_WRDATA_EN_P2[63:0]InputDFI write data and data mask enable
DFI_WRDATA_EN_P3[63:0]InputDFI write data and data mask enable
DFI_WRDATA_MASK_P0[15:0]1InputDFI write data byte mask
DFI_WRDATA_MASK_P1[15:0]1InputDFI write data byte mask
DFI_WRDATA_MASK_P2[15:0]1InputDFI write data byte mask
DFI_WRDATA_MASK_P3[15:0]1InputDFI write data byte mask
DFI_WRDATA_P0[127:0]1InputThese signals transfer write Data from memory controller to PHY
DFI_WRDATA_P1[127:0]1InputThese signals transfer write Data from memory controller to PHY
DFI_WRDATA_P2[127:0]1InputThese signals transfer write Data from memory controller to PHY
DFI_WRDATA_P3[127:0]1InputThese signals transfer write Data from memory controller to PHY
Note:
  1. Depends on DQ width (see Table 2-23 and Table 2-24).
Table 2-18. DFI Read Data Interface
Signal NameDirectionDescription
DFI_RDDATA_CS_N_P0[0]InputDFI read data chip select
DFI_RDDATA_CS_N_P1[0]InputDFI read data chip select
DFI_RDDATA_CS_N_P2[0]InputDFI read data chip select
DFI_RDDATA_CS_N_P3[0]InputDFI read data chip select
DFI_RDDATA_EN_P0[63:0]1InputDFI read data enable
DFI_RDDATA_EN_P1[63:0]1InputDFI read data enable
DFI_RDDATA_EN_P2[63:0]1InputDFI read data enable
DFI_RDDATA_EN_P3[63:0]1InputDFI read data enable
DFI_RDDATA_VALID_W0[7:0]1OutputDFI read data valid
DFI_RDDATA_VALID_W1[7:0]1OutputDFI read data valid
DFI_RDDATA_VALID_W2[7:0]1OutputDFI read data valid
DFI_RDDATA_VALID_W3[7:0]1OutputDFI read data valid
DFI_RDDATA_W0[127:0]1OutputDFI read data
DFI_RDDATA_W1[127:0]1OutputDFI read data
DFI_RDDATA_W2[127:0]1OutputDFI read data
DFI_RDDATA_W3[127:0]1OutputDFI read data
Note:
  1. Depends on DQ width (see Table 2-23 and Table 2-24).
Table 2-19. DFI Write Calibration Interface
Signal NameDirectionDescription
CAL_L_BUSYInputWrite Calibration Busy. Indicates this interface is not accepting new commands. A command is accepted when CAL_L_R_REQ or CAL_L_W_REQ is set and CAL_L_BUSY is low.
CAL_L_DATAOUT[511:0]1InputWrite calibration data output from the controller

Depends on DQ width.

CAL_L_D_REQInputWrite calibration data request from the controller.
CAL_L_R_VALIDInputWrite calibration read valid from the controller.
CAL_L_DATAIN[511:0]1OutputWrite calibration data input to the controller

Depends on DQ width.

CAL_L_DM_IN[63:0]1OutputWrite calibration data mask input to the controller

Depends on DQ width.

CAL_L_R_REQOutputWrite calibration read request to the controller.
CAL_L_W_REQOutputWrite calibration write request to the controller.
CAL_SELECTOutputWrite Calibration Select to the controller.
CAL_INIT_ACK2InputCalibration initialization bus available handshake from DDR controller.
CAL_INIT_CS[1:0]2OutputCalibration initialization bus chip select.
CAL_INIT_MR_ADDR[7:0]2OutputCalibration initialization bus mode register write address.
CAL_INIT_MR_DATA[17:0]2OutputCalibration initialization bus mode register write data.
CAL_INIT_MR_MASK[17:0]2OutputCalibration initialization bus mode register write mask.
CAL_INIT_MR_W_REQ2OutputCalibration initialization bus mode register write request.
Note:
  1. Depends on DQ width (see Table 2-23 and Table 2-24).
  2. These ports are only for DDR4.
  3. The DRAM interface is same as Table 2-15 for DDR PHY only solution.
Table 2-20. DFI Training Interface
Signal NameDirectionDescription
DFI_RDLVL_CS_N[0]InputChip select for read data eye training
DFI_RDLVL_ENInputPHY read data eye training enable
DFI_RDLVL_GATE_ENInputPHY read gate training enable
DFI_WRLVL_CS_N[0]InputChip select for write leveling
DFI_WRLVL_ENInputPHY write leveling logic enable
DFI_WRLVL_STROBEInputInitiates capture of write level response
DFI_RDLVL_RESP[7:0]OutputIndicates data eye or gate training complete
DFI_WRLVL_RESP[7:0]OutputIndicates PHY has completed write leveling
Table 2-21. DFI Status Interface
Signal NameDirectionDescription
DFI_INIT_STARTInputDFI setup stabilization
DFI_INIT_COMPLETEOutputPHY initialization complete
Table 2-22. DFI Clock and Miscellaneous
Signal NameDirectionDescription
PLL_LOCKOutputPLL lock indicator
PLL_REF_CLKInputPLL reference clock
SYS_CLKOutputPLL system clock output to controller
SYS_RESET_NInputGlobal reset input
SYNC_SYS_RST_NOutputSynchronized reset output
CTRLR_READY_INInputController ready status from controller to PHY
CTRLR_READY_OUTOutputController ready status from PHY to controller
DFI_TRAINING_COMPLETEOutputPHY output to controller to indicate training complete