The PLL can be used to increase the frequency of the clock source defined by the SOURCE bit in the PLL Control A (CLKCTRL.PLLCTRLA) register. The minimum input frequency of the PLL is 16 MHz, and the maximum output frequency is 48 MHz.
1
’, indicating that the PLL has locked in on the desired
frequency.For available connections, refer to the CLKCTRL Block Diagram figure in the Clock Controller (CLKCTRL) section.