Features
- AVR® CPU
- Running at up to 24 MHz
- Single-cycle I/O register
access
- Two-level interrupt
controller
- Two-cycle hardware
multiplier
- Supply voltage range: 1.8V to 5.5V
- Memories
-
32 KB In-System
self-programmable Flash memory
- 512B EEPROM
-
4 KB SRAM
- 32B of user row in nonvolatile memory that
can keep data during chip-erase and be programmed while the device is
locked
- Write/erase endurance
- Flash: 10,000
cycles
- EEPROM: 100,000
cycles
- Data retention: 40 Years at
55°C
- System
- Power-on Reset (POR) circuit
- Brown-out Detector (BOD) with
user-programmable levels
- Voltage Level Monitor (VLM)
with interrupt at a programmable level above the BOD level
- Clock failure detection
- Clock options
- High-precision
internal oscillator with selectable frequency up to 24 MHz (OSCHF)
- Auto-tuning
for improved internal oscillator accuracy
- Internal PLL up to
48 MHz for high-frequency
operation of Timer/Counter type D (PLL)
- Internal ultra-low
power 32.768 kHz oscillator (OSC32K)
- External 32.768 kHz
crystal oscillator (XOSC32K)
- External clock
input
- External
high-frequency crystal oscillator (XOSCHF) with clock failure
detection
- Single pin Unified Program and Debug
Interface (UPDI)
- Three sleep modes
- Idle with all
peripherals running for immediate wake-up
- Standby with a configurable operation of
selected peripherals
- Power-Down with full
data retention
- Peripherals
- Up to two 16-bit
Timer/Counters type A (TCA) with three compare channels for PWM and waveform
generation
- Up to
four
16-bit Timer/Counters type B (TCB) with input capture for capture and signal measurements
- One 12-bit PWM Timer/Counter
type D (TCD) optimized for power control
- One 16-bit Real-Time Counter
(RTC) that can run from external crystal or internal oscillator
- Up to
five USARTs
- Operation modes:
RS-485, LIN client, host SPI, and IrDA
- Fractional baud rate
generator, auto-baud, and start-of-frame detection
- Two SPIs with host/client
operation modes
- Up to two Two-Wire Interface
(TWI) with dual address match
- Independent host and client operation Dual
mode)
- Phillips
I2C compatible
- Standard mode (Sm,
100 kHz)
- Fast mode (Fm, 400
kHz)
- Fast mode plus (Fm+,
1 MHz)(1)
- Event System for CPU-independent and
predictable inter-peripherals signaling
- Configurable Custom Logic
(CCL) with up to six programmable Look-up Tables (LUTs)
- One 12-bit 130 ksps differential Analog-to-Digital Converter
(ADC)
- Three Analog Comparators
(ACs) with window compare functions
- One 10-bit Digital-to-Analog
Converter (DAC)
- Up to
two Zero-Cross Detectors (ZCDs)
- Analog Signal Conditioning
(OPAMP) peripheral with up to three op amps, each with an internal resistor
ladder that allows for many useful configurations with no external
components
- Multiple voltage references
(VREF)
- 1.024V
- 2.048V
- 2.500V
- 4.096V
- External Voltage
Reference (VREFA)
- Supply Voltage
(VDD)
- Automated Cyclic Redundancy
Check (CRC) Flash program memory scan
- Watchdog Timer (WDT) with
Window mode, and separate on-chip oscillator
- External interrupt on all
general purpose pins
- I/O and Packages
- Multi-Voltage I/O (MVIO) on
I/O port C
- Selectable input voltage
threshold
-
Up to 41/40 programmable I/O
pins
- 28-pin SSOP, SOIC and
SPDIP
- 32-pin VQFN 5x5 mm and TQFP
7x7 mm
- 48-pin VQFN 5x5 mm and TQFP
7x7 mm
- Temperature Ranges
- Industrial: -40°C to
85°C
- Extended: -40°C to 125°C
Note:
- 1.I2C Fm+ is only supported for
supply voltage VDD above 2.7 VDC.