If it is impossible to achieve the desired frequency because of the prescaler/period selection limitations, dithering can be used to approximate the desired frequency and reduce the waveform drift.

The dither accumulates the fractional error of the counter clock for each cycle. When the fractional error overflows, an additional clock cycle is added to the selected part of the TCD cycle.

Generate 75 kHz from a 10 MHz Clock

If the timer clock frequency is 10 MHz, it will give the timer a resolution of 100 ns. The desired output frequency is 75 kHz, which means a period of 13,333 ns. This period cannot be achieved with a 100 ns resolution as it would require 133.33 cycles. The output period can be set to either 133 cycles (75.188 kHz) or 134 cycles (74.626 kHz).

It is possible to change the period between the two frequencies manually in the firmware to get an average output frequency of 75 kHz (change every third period to 134 cycles). The dither can do this automatically by accumulating the error (0.33 cycles). The accumulator calculates when the accumulated error is larger than one clock cycle. When that happens, an additional cycle is added to the timer period.

Figure 1. Dither Logic
The user can select where in the TCD cycle the dither will be added by writing to the Dither Selection (DITHERSEL) bit field in the Dither Control (TCDn.DITCTRL) register:

How much the dithering will affect the TCD cycle time depends on what Waveform Generation mode is used (see Table 1). Dithering is not supported in Dual Slope mode.

Table 1. Mode-Dependent Dithering Additions to TCD Cycle
WAVEGEN DITHERSEL in TCDn.DITCTRL Additional TCD Clock Cycles to TCD Cycle
One Ramp mode On-time B 1
On-time A and B 1
Dead-time B 0
Dead-time A and B 0
Two Ramp mode On-time B 1
On-time A and B 2
Dead-time B 0
Dead-time A and B 0
Four Ramp mode On-time B 1
On-time A and B 2
Dead-time B 1
Dead-time A and B 2
Dual Slope mode On-time B Not supported
On-time A and B Not supported
Dead-time B Not supported
Dead-time A and B Not supported

The differences in the number of TCD clock cycles added to the TCD cycle are caused by the different number of compare values used by the TCD cycle. For example, in One Ramp mode, only CMPBCLR affects the TCD cycle time.

For DITHERSEL configurations where no extra cycles are added to the TCD cycles, compensation is reached by shortening the following output state.

DITHERSEL in One Ramp Mode

In One Ramp mode with DITHERSEL selecting dead-time B, the dead-time B will be increased by one cycle when dither overflow occurs, reducing on-time B by one cycle.