Instruction Execution Timing

The AVR CPU is clocked by the CPU clock, CLK_CPU. No internal clock division is applied. The figure below shows the parallel instruction fetches and executions enabled by the Harvard architecture and the fast-access register file concept. This is a two-stage pipelining concept enabling up to 1 MIPS/MHz performance with high efficiency.

Figure 1. The Parallel Instruction Fetches and Executions