Figure 1. CLKCTRL Block Diagram
The clock system consists of the main clock and clocks derived from the main clock,
as well as several asynchronous clocks:
- Main Clock (CLK_MAIN) is always
running in Active and Idle sleep modes. If requested, it will also run in
Standby sleep mode.
- CLK_MAIN is prescaled and distributed by the clock controller:
- CLK_CPU is used by the
CPU and the Nonvolatile Memory Controller (NVMCTRL) peripheral
- CLK_PER is used by SRAM
and all peripherals that are not listed under asynchronous clocks and
can also be routed to the CLKOUT pin
- All the clock sources can
be used as the main clock
- Clocks running asynchronously to
the main clock domain:
- CLK_RTC is used by the
Real-Time Counter (RTC) and the Periodic Interrupt Timer (PIT). It will
be requested when the RTC/PIT is enabled. The clock source for CLK_RTC
may be changed only if the peripheral is disabled.
- CLK_WDT is used by the
Watchdog Timer (WDT). It will be requested when the WDT is enabled.
- CLK_BOD is used by the
Brown-out Detector (BOD). It will be requested when the BOD is enabled
in Sampled mode. The alternative clock source is controlled by a
fuse.
- CLK_TCD is used by the Timer Counter type D
(TCD). It will be requested when the TCD is enabled. The clock source
may be changed only if the peripheral is disabled.
- Clock Failure Detector
(CFD) is an asynchronous mechanism to detect a failure on an external
crystal or clock source
The clock source for the main clock domain is configured by writing to the Clock Select
(CLKSEL) bit field in the Main Clock Control A (CLKCTRL.MCLKCTRLA) register. This
register has Configuration Change Protection (CCP), and the appropriate key must be
written to the CCP register before writing to the CLKSEL bit field. The asynchronous
clock sources are configured by the registers in the respective peripheral.