48.6.3.5 25-bit to 32-bit Data

When SPDIFTX_MR.BPS=3, SPDIFTX_MR.CMODE must be configured to 3.

Due to the 24-bit data definition of the IEC standard, the data written in SPDIFTX_CDR is first shifted by 8 bits before being sent. In this mode, VPBS must be at least equal to 24.

Figure 48-16. Sending a 4-Byte Data Defined on 26 Bits

In the following figures, A_x represents the x^th byte of channel 1 and A₀ is the least significant byte of A. B_x represents the x^th byte of channel 2 and B₀ is the least significant byte of B.

Figure 48-17. SPDIFTX_CDR Organization when SPDIFTX_MR.BPS=3