48.6.3.4 17-bit to 24-bit Data

When SPDIFTX_MR.BPS=2, the data organization depends on the value of SPDIFTX_MR.CMODE.

When the size of the data to transmit is lower than or equal to 24 bits, this operating mode reduces the system bus bandwidth required to transfer the buffer of data.

When CMODE=0, the destination of the data in SPDIFTX_CDR depends on the value of the MSB [31:24] of SPDIFTX_CDR.CDR. If CDR[31:24]=0, the data is sent to channel 1. If CDR[31:24]=1, the data is sent to channel 2.

The 3-byte justified data written in SPDIFTX_CDR.CDR[23:0] is transmitted on the SPDIF line.

Figure 48-11. Transmitting 24-bit Oriented Data Carrying 20 Valid Bits

In the following figures, Ax represents the xth byte of channel 1 and A0 is the least significant byte of A. Bx represents the xth byte of channel 2 and B0 is the least significant byte of B.

Figure 48-12. SPDIFTX_CDR Organization when SPDIFTX_MR.CMODE=0

When SPDIFTX_MR.CMODE=1, data are sent alternately on channel 1 and channel 2. The first sent data is sent to channel 1 (even cycles), the following data is sent to channel 2 (odd cycles).

Figure 48-13. SPDIFTX_CDR Register Organization when SPDIFTX_MR.CMODE=1
When SPDIFTX_MR.CMODE=2, the write access to SPDIFTX_CDR is optimized for 24-bit data samples being compacted on 32 bits.
  • The first access to SPDIFTX_CDR contains the data for channel 1 on CDR[23:0]. CDR[31:24] contain part of the data for channel 2.
  • The second access contains the remaining data of channel 2 (CDR[15:0]). CDR[31:16] contain part of the data to send to channel 1.
  • The third access contains CDR[7:0] remaining data for channel 1. CDR[31:8] contain the data to be sent to channel 2.

The total size of the data to send must be an integer multiple of 3 so that there is no interference between channels.

Figure 48-14. SPDIFTX_CDR Organization when SPDIFTX_MR.CMODE=2

When SPDIFTX_MR.CMODE=3, SPDIFTX_CDR.CDR[23:0] contains only one 24-bit data and CDR[31:24] contains SPDIF frame control bits.

Depending on the configuration of SPDIFTX_EMR, the control bits supplied in the MSB byte are used or not. When SPDIFTX_MR.CMODE=3, the User Data, Channel Status, validity bit and parity error are managed on a per data basis. If SPDIFTX_EMR.PCM is set, the preamble is no longer set automatically by the SPDIFTX; the preamble type is selected using SPDIFTX_CDR.PC instead.

Figure 48-15. SPDIFTX_CDR Organization when SPDIFTX_MR.CMODE=3 Mode