48.6.3.2 Up to 8-bit Data

When SPDIFTX_MR.BPS=0, each write access to SPDIFTX_CDR provides up to four data samples.

When the size of the data to transmit is lower than or equal to 8 bits, this operating mode reduces the system bus bandwidth required to transfer the buffer of data.

When SPDIFTX_MR.MULTICH=1 (stereo channels, etc.), two data (e.g. 2 stereo audio samples) are written per access to SPDIFTX_CDR. When SPDIFTX_MR.MULTICH=0 (MONO), four data (e.g. 4 mono audio samples) are written per SPDIFTX_CDR access.

When SPDIFTX_MR.BPS=0, the SPDIFTX_MR.ENDIAN bit has no effect.

The first byte sent is located on the LSB part of the SPDIFTX_CDR register.

When necessary, the SPDIFTX_CDR byte to send is MSB-aligned on the 24-bit data word transmitted on the SPDIF line.

In the following figures, A_x represents the x^th byte of channel 1 and A₀ is the least significant byte of A. B_x represents the x^th byte of channel 2 and B₀ is the least significant byte of B.

When SPDIFTX_MR.MULTICH=0, each byte of channel 1 is duplicated on channel 2

In SPDIFTX_MR.MULTICH=1, bytes are sent alternately to channel 1 and channel 2.