48.6.3.1 Automatic Data Alignment

When the number of valid bits in the data to be transmitted is smaller than the size of the container (VPBS < 8*(BPS+1)), the SPDIFTX must be instructed with the justification of the received data (data written in SPDIFTX_CDR).

SPDIFTX_MR.JUSTIFY defines the alignment of the valid bits per sample (defined by VPBS) of the data written in SPDIFTX_CDR.CDR.

If the valid bits are MSB-aligned in the container, SPDIFTX_MR.JUSTIFY=1.

If the valid bits are LSB-aligned in the container, SPDIFTX_MR.JUSTIFY=0.

When necessary, the SPDIFTX automatically realigns CDR data. The automatic realignment prevents software intervention or manipulation on the data buffer prior to writing the SPDIFTX_CDR.

There is no alignment when the number of valid bits per sample configured in VPBS is equal to the size of the container configured in BPS (VPBS = 8*(BPS+1)).

VBPS must be less than or equal to 8 times the number of bytes defined in BPS (VBPS ≤ 8*(BPS+1)).