48.6.3.3 9-bit to 16-bit Data

When SPDIFTX_MR.BPS=1, each write access to SPDIFTX_CDR provides two data samples.

When the size of the data to transmit is lower than or equal to 16 bits, this operating mode reduces the system bus bandwidth required to transfer the buffer of data.

The data of channel 1 is located in SPDIFTX_CDR.CDR[15:0]. SPDIFTX_CDR.CDR[31:16] are loaded by either the next data to send (mono channel) or the data of channel 2 (stereo channels).

When necessary, the SPDIFTX_CDR half-word to send is MSB-aligned on the 24-bit data word transmitted on the SPDIF line.

Figure 48-8. Transmitting Halfword-Oriented Data Carrying 10 Valid Bits

In the following figures, A_x represents the x^th byte of channel 1 and A₀ is the least significant byte of A. B_x represents the x^th byte of channel 2 and B₀ is the least significant byte of B.

The byte organization of data depends on the configuration of SPDIFTX_MR.ENDIAN.

Figure 48-9. SPDIFTX_CDR Organization for BYTE2, Mono Mode

Figure 48-10. SPDIFTX_CDR Organization for BYTE2, Dual Mode