12.2.4 ASIB QoS Control Register
| Name: | NICGPV_ASIB_QOS_CNTLx |
| Offset: | 0x04210C + x*0x1000 [x=0..10] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MODE_AR_FC | MODE_AW_FC | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN_AWAR_OT | EN_AR_OT | EN_AW_OT | EN_AR_FC | EN_AW_FC | EN_AWAR_RATE | EN_AR_RATE | EN_AW_RATE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 20 – MODE_AR_FC AR Feedback Control Mode
Select feedback control regulation for AR of either transaction or address latency.
0 (TRANS_LAT): Transaction latency
1 (ADDR_LAT): Address latency
Bit 16 – MODE_AW_FC AW Feedback Control Mode
Select feedback control regulation for AW of either transaction or address latency.
0 (TRANS_LAT): Transaction latency
1 (ADDR_LAT): Address latency
Bit 7 – EN_AWAR_OT AWAR Outstanding Transactions Enable
0 (DISABLED): Disable combined regulation of outstanding transactions.
1 (ENABLED): Enable combined regulation of outstanding transactions.
Bit 6 – EN_AR_OT AR Outstanding Transactions Enable
0 (DISABLED): Disable regulation of outstanding read transactions.
1 (ENABLED): Enable regulation of outstanding read transactions.
Bit 5 – EN_AW_OT AW Outstanding Transactions Enable
0 (DISABLED): Disable regulation of outstanding write transactions.
1 (ENABLED): Enable regulation of outstanding write transactions.
Bit 4 – EN_AR_FC AR Feedback Control Enable
0 (DISABLED): Disable regulation of AR transaction or address latency.
1 (ENABLED): Enable regulation of AR transaction or address latency using feedback control, depending on the MODE_AR_FC setting.
Bit 3 – EN_AW_FC AW Feedback Control Enable
0 (DISABLED): Disable regulation of AW transaction or address latency.
1 (ENABLED): Enable regulation of AW transaction or address latency using feedback control, depending on the MODE_AW_FC setting.
Bit 2 – EN_AWAR_RATE AW and AR Rates Enable
0 (DISABLED): Disable combined AW and AR rate regulation.
1 (ENABLED): Enable combined AW and AR rate regulation.
Bit 1 – EN_AR_RATE AR Rate Enable
0 (DISABLED): Disable AR rate regulation.
1 (ENABLED): Enable AR rate regulation.
Bit 0 – EN_AW_RATE AW Rate Enable
0 (DISABLED): Disable AW rate regulation.
1 (ENABLED): Enable AW rate regulation.