12.2.13 ASIB Feedback Controlled Target Register

This register is used to program a target latency, in cycles, for the regulation of reads and writes.

Name:	NICGPV_ASIB_TARGET_FCx
Offset:	0x042130 + x*0x1000 [x=0..10]
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
					AR_TGT_LATENCY[11:8]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
	AR_TGT_LATENCY[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
					AW_TGT_LATENCY[11:8]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	AW_TGT_LATENCY[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 27:16 – AR_TGT_LATENCY[11:0] AR Channel Target Latency

Bits 11:0 – AW_TGT_LATENCY[11:0] AW Channel Target Latency

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