17.4.6 Velocity Counter
The Velocity Counter (VELxCNT) is a register that is up to 32 bits wide and increments or decrements based on the signal from the quadrature decoder logic. Reading this register results in a counter Reset. The Index input or any of the modes specified by the PIMOD[2:0] bits in the QEIx Control register (QEIxCON[12:10]) do not affect the operation of the Velocity Counter. If the Velocity Counter rolls over from 0x7FFF to 0x8000, or from 0x8000 to 0x7FFF, and the VELOVIEN bit in the QEIx Status register (QEIxSTAT[4]) is set, an interrupt will be generated. Figure 17-6 illustrates the timing diagram of the Velocity Counter operation.
Note: The Velocity Counter specifies the distance traveled between the
time interval of each sample. Reading the VELxCNT register results in a counter Reset. The
user application should read the Velocity Counter at a rate of 1-4 kHz.