17.4.5 Internal Timer Mode

In this mode, the Position Counter, Velocity, Index and Interval Counters use an internal clock as the count source. The internal clock is divided by the clock divider using the INTDIV[2:0] bits in the QEIx Control register (QEIxCON[6:4]). If the GATEN bit in the QEIx Control register (QEIxCON[2]) is set and QEBx/DIR/GATE = 0, the QEBx/DIR/GATE input will inhibit the counter signal. If the GATEN bit is cleared, the gate signal does not affect the operation of the counter. The default count direction is positive. If the CNTPOL bit in the QEIx Control register (QEIxCON[3]) is set, the count direction is negative. Figure 17-5 illustrates the timing diagram of an Internal Timer mode operation.

The INDEX input enables and disables (gates) the counting of the Index Counter. The HOME input enables and disables (gates) the counting of the Interval Counter.