16.4.1.6 Digital Filter

In many motor and power control applications, the analog comparator input signals can be corrupted by the large electromagnetic fields generated by the external switching power transistors. Corruption of the analog input signals to the comparator can cause unwanted comparator output transitions. A digital output filter can minimize the effects of the input signal corruption. The digital filter processes the comparator signal from the pulse stretcher circuit. The digital filter is enabled by the FLTREN bit (DACxCON[8]). The digital filter operates with the different clock divider selected by the FCLKDIV[2:0] bits (DACCTRL1[2:0]). The pulse stretcher output signal must be stable, either in a high state or a low state, for at least three times the selected filter clock frequency for it to pass through the digital filter. Assuming the current state is ‘0’, a comparator output string of ‘0011110000000000’ gets modified by the pulse stretcher to ‘0011111100000000’ and to ‘0000000001111110’ by the digital filter if the filter clock frequency is divided by two. Because of the requirement of three similar consecutive states for the filter, the selected digital filter clock period must be one third or less than the maximum desired comparator response time. In Sleep mode or Idle mode, the digital filter is bypassed to enable an asynchronous signal from the comparator to the interrupt controller. This asynchronous signal can be used to wake-up the processor from Sleep mode or Idle mode. A configuration example to enable the digital filter is provided in Configuration for Digital Filter.

DACCTRL1bits.FCLKDIV = 1;	 	 	       /* Filter Clk Divide by 2 */
DAC1CONbits.FLTREN = 1;   	 	 	 	 /* Filter enabled */