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High-Performance dsPIC33A Core with Floating-Point Unit, High-Speed ADCs and High-Resolution PWM
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16
High-Speed Analog Comparator with Slope Compensation DAC
16.4
Operation
16.4.1
Comparator Stage
dsPIC33AK128MC106
Product Family
Pin Diagrams
Pinout I/O Descriptions
Terminology Cross Reference
1
Device Overview
2
Guidelines for Getting Started with Digital Signal Controllers
3
CPU
4
Memory Organization
5
Data Memory
6
Flash Program Memory
7
Configuration Bits
8
Security Module
9
Resets
10
Interrupt Controller
11
I/O Ports with Edge Detect
12
Oscillator and Clocking Module
13
Direct Memory Access (DMA) Controller
14
High-Resolution Pulse-Width Modulation (PWM)
15
High-Speed, Low Latency ADC
16
High-Speed Analog Comparator with Slope Compensation DAC
16.1
Device-Specific Information
16.2
Architectural Overview
16.3
Register Summary
16.4
Operation
16.4.1
Comparator Stage
16.4.1.1
Comparator Inputs
16.4.1.2
Comparator Outputs
16.4.1.3
Comparator Interrupt
16.4.1.4
Comparator Hysteresis Control
16.4.1.5
Pulse Stretcher
16.4.1.6
Digital Filter
16.4.2
Pulse Density Modulation (PDM) DAC
16.4.3
Operation in Sleep and Idle Mode
16.4.4
Calibration
16.5
Application Examples
17
Quadrature Encoder Interface (QEI)
18
Universal Asynchronous Receiver Transmitter (UART)
19
Serial Peripheral Interface (SPI)
20
Inter-Integrated Circuit (I
2
C)
21
Single-Edge Nibble Transmission (SENT)
22
Bidirectional Serial Synchronous (BiSS) Module
23
Timer1
24
Single-Output Capture/Compare/PWM/Timer Modules (SCCP)
25
Configurable Logic Cell (CLC)
26
Peripheral Trigger Generator (PTG)
27
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
28
Current Bias Generator (CBG)
29
Operational Amplifier (Op Amp)
30
Watchdog Timer (WDT)
31
Deadman Timer (DMT)
32
Device Power-Saving Modes
33
JTAG Interface
34
In-Circuit Debugger
35
Instruction Set Summary
36
Development Support
37
Electrical Characteristics
38
High-Temperature Electrical Characteristics
39
Packaging Information
40
Revision History
41
Product Identification System
Microchip Information
16.4.1 Comparator Stage
