16.4.2 Pulse Density Modulation (PDM) DAC
Each instance of the High-Speed Analog Comparator with Slope Compensation DAC has a dedicated DAC that is used to program the comparator threshold voltage via the DACxDAT register. The DAC comprises a digital Pulse Density Modulation (PDM) module, followed by a multistage RC filter. The PDM module generates a high-frequency output signal whose density is proportional to the DACxDAT register value.
The DACxDAT register values have limits of 0x0CD and 0xF32 and will provide a DAC output of 5% to 95% of AVDD. For any intermediate value in the register, between 0xCD and 0xF32, the output voltage of the DAC will be proportional. The equation to calculate the DAC output voltage based on the AVDD voltage source is provided in DACxDAT. The DAC voltage can be varied in steps of AVDD/(2N – 1), where N is the number of DAC bits (N = 12). The DAC modules are controlled by the DACON bit (DACCTRL1[15]). The DACON bit enables or disables all of the comparator modules instantiated on a given device or device core. The DACEN bit (DACxCON[15]) provides individual control of the DAC module. The individual DAC registers have an output enable bit, DACOEN (DACxCON[9]), which enables the DAC output voltage to be routed to an external output pin, DACOUT1. A configuration example to set the DAC output voltage is shown in Configuration of DAC Register.
Where: 0x0CD ≤ DACDATx ≤ 0xF32
Configuration of DAC Register
/* DAC Register Settings */
DAC1DATbits.DACDAT = 0x4D9; /* DAC Output set to 1V (AVDD = 3.3V)*/
DAC1CONbits.DACOEN = 1; /* Enable DAC 1 output on pin DACOUT1 */
DAC1CONbits.DACEN = 1; /* Enable DAC 1 */
DACCTRL1bits.DACON = 1; /* Turn ON all DACs */