13.6.1.3 Overrun Interrupt

When a DMA channel receives a trigger while its CHREQ bit is already set (either by software or another hardware trigger), an Overrun condition occurs. This condition indicates that the channel is being requested before its current transaction is finished. This implies that the active channel may not be able to keep up with the demands from the peripheral module being serviced, which may result in data loss. An Overrun condition causes the OVERRUN flag (DMAxSTAT[3]) to be set.

Note that the OVERRUN flag being set does not cause the current DMA operation to terminate. Therefore, the channel for which OVERRUN is set does not need to be the active channel.

Setting the priority scheme correctly also helps to avoid overrun errors. For example, if one of the channels operates more frequently, a Fixed Priority scheme with that as the channel will help to reduce overrun interrupts.