22.3.5.5 Memory Bank Switching

Since BiSS can operate at high speeds of transmission, the BiSS module incorporates memory bank switching. The BiSS module has two memory banks. The status of which memory bank is active can be read by monitoring the BANKSEL bit. It is critical that the registers are not written to during bank switching; therefore, there is also a register access bit to monitor if registers are currently being accessed. By default, bank switching is enabled, but the user can disable it using the SBANK bit. The bank switching feature is also able to hold the bank switch during reads to confirm that data integrity is maintained. There is also the ability to manually switch banks with the SWBANK bit. These bits combine to allow for different ways to maintain control of the module’s bank switching.