I2S Audio Host Mode of Operation Using REFCLKO

The following steps can be used to set up the SPI module for the I2S Audio Host mode of operation. The SPI module is initialized to generate BCLK @ 625 kbps and MCLK is derived using the REFO module. To configure the REFO module, refer to Reference Clock Output (REFOx). A typical application could be to play PCM data (8 kHz sample frequency, 16-bit data, 32-bit frame) when interfaced to a codec client device.

  1. If using interrupts, disable the SPIx interrupts in the respective IECx register.
  2. Stop and reset the SPI module by clearing the ON bit (SPIxCON1[15]).
  3. Reset the SPIx Control Register 1, SPIxCON1.
  4. Reset the SPIx Baud Rate Register, SPIxBRG.
  5. Clear the receive buffer.
  6. Clear the ENHBUF bit (SPIxCON1[0]) if using Standard Buffer mode or set the bit if using Enhanced Buffer mode.
  7. If using interrupts, the following additional steps are performed:
    1. Clear the SPIx interrupt flags/events in the respective IFSx register.
    2. Write the SPIx interrupt priority and sub-priority bits in the respective IPCx register.
    3. Set the SPIx interrupt enable bits in the respective IECx register.
    4. Clear the SPIROV bit (SPIxSTAT[6]).
  8. Write the desired settings in the SPIxCON1 register. The AUDMOD[1:0] bits (SPIxCON1[25:24]) must be set to ‘00’ for I2S mode and the AUDEN bit (SPIxCON1[31]) must be set to ‘1’ to enable the audio protocol.
  9. Set the Reference Oscillator Controller register; to configure the REFO module, refer to Reference Clock Output (REFOx).
  10. Set the SPIx Baud Rate Register, SPIxBRG, to 0x0F (to generate approximately 625 kbps sample rate with SPICLK @ 20 MHz).
  11. Write the desired settings to the SPIxCON1 register with:
    1. MSTEN (SPIxCON1[5]) = 1.
    2. CKP (SPIxCON1[6]) = 1.
    3. MODE[32,16] (SPIxCON1[11:10]) = 0 for 16-bit audio channel data.
    4. MCLKEN (SPIxCON1[2]) = 1, Host mode.
    5. Enable SPI operation by setting the ON bit (SPIxCON1[15]).
  12. Transmission (and reception) will start as soon as the host provides the BCLK and LRCK.
Note: The use of a reference clock output to generate MCLK for the codec may not be a perfect choice. Driving a clock out to an I/O pad induces a jitter that may degrade audio fidelity of the codec. The best solution is for the codec to use a crystal and be the host I2S/audio device.

I2S Host Mode, 625 kbps BCLK, 16-Bit Channel Data, 32-Bit Frame

/* The following code example will initialize the SPI1 Module in I2S Maaster mode.
_SPI1TXIP = 4;
SPI1STATbits.SPIROV = 0;      // clear the Overflow
SPI1BRG = 0x000F;             // to generate 625 kbps sample rate, SPICLK @ 20 MHz
SPI1CON1 = 0x80000464;        // AUDEN=1, I2S mode, stereo mode,
                              // 16 bits/32 channel transfer,
Host mode,ckp=1,
SPI1IMSKbits.SPITBFEN = 1;    // SPI1 transmit buffer full generates interrupt event
_SPI1TXIE = 1;                // Enable interrupts
_SPI1RXIE = 1;
SPI1CON1bits.ENHBUF = 1;
SPI1CON1bits.ON = 1;
// from here, the device is ready to receive and transmit data