20.5.4.5 Sending Data to a Host Device

When the R/W status bit of the incoming device address byte is ‘1’ and an address match occurs, the R/W status bit (I2CxSTAT1[2]) is set. At this point, the host device is expecting the client to respond by sending a byte of data. The contents of the byte are defined by the system protocol and are only transmitted by the client.

When the interrupt from the address detection occurs, the user software can write a byte to the I2CxTRN register to start the data transmission.

The client sets the TBF status bit (I2CxSTAT1[0]). The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time. When all eight bits have been shifted out, the TBF status bit is cleared.

The client detects the Acknowledge from the host-receiver on the rising edge of the ninth SCLx clock.

If the SDAx line is low, indicating an ACK, the host is expecting more data and the message is not complete. The module generates a client interrupt and the ACKSTAT status bit (I2CxSTAT1[15]) can be inspected to determine whether more data is being requested.

A client interrupt is generated on the falling edge of the ninth SCLx clock. User software must check the status of the I2CxSTAT register and clear the I2CxIF interrupt flag if the CDTXIE (I2CxINTC[3]) bit and CSTIE(I2CxINTC[12]) are enabled.

If the SDAx line is high, indicating a NACK, the data transfer is complete. User software should not write further data to the I2CxTRN register. The client resets and generates an interrupt, and it waits for detection of the next Start bit.