20.5.4.5.1 Wait States During Client Transmissions

During a client transmission message, the host expects return data immediately after detection of the valid address with R/W = 1. Because of this, the client automatically generates a bus Wait whenever the client returns data.

The automatic Wait occurs at the falling edge of the ninth SCLx clock of a valid device address byte or transmitted byte, Acknowledged by the host, indicating expectation of more transmit data.

The client clears the SCLREL bit (I2CxCON1[12]). Clearing the SCLREL bit causes the client to pull the SCLx line low, initiating a Wait. The SCLx clock of the host and client will synchronize, as shown in Host Clock Synchronization.

When the user software loads the I2CxTRN register and is ready to resume transmission, the user software sets the SCLREL bit. This causes the client to release the SCLx line, and the host resumes clocking.

Note: The user software must provide a delay between writing to the transmit buffer and setting the SCLREL bit. This delay must be greater than the minimum setup time for client transmissions, as specified in the “Electrical Characteristics” chapter.