20.5.4.4 Receiving Data from a Host Device

When the R/W status bit of the device address byte is ‘0^’ and an address match occurs, the R/W status bit (I2CxSTAT1[2]) is cleared. The client enters a state waiting for data to be sent by the host. After the device address byte, the contents of the data byte are defined by the system protocol and are only received by the client. User software should configure data packet size in PSZ (I2CxCON2).

The client shifts eight bits into the I2CxRSR register. On the falling edge of the eighth clock (SCLx), the following events occur:

• The module begins to generate an ACK or NACK.
• The RBF status bit (I2CxSTAT1[1]) is set to indicate received data.
• The I2CxRSR register byte is transferred to the I2CxRCV register for access by the user software.
• The D/A status bit is set.
• A client interrupt is generated. User software can check the status of the I2CxSTAT register to determine the cause of the event and then clear the I2CxIF interrupt flag if the CDRXIE (I2CxINTC[4]) bit and CSTIE (I2CxINTC[12]) are enabled.
• The module waits for the next data byte.
• Once packet size becomes zero, end of packet (EOP) will be set (I2CxSTAT2[24]).