15.4.13.1 Sleep and Idle Modes

When a device enters Sleep mode, the system oscillator (F_OSC) and all components that operate from it are halted. This includes the ADC when F_OSC is selected for the clock source. When Sleep mode is invoked during a conversion with F_OSC as the clock source, the conversion is aborted. The converter will not resume a partially completed conversion upon exiting from Sleep mode. The ADC register contents are not affected by the device entering or leaving Sleep mode.

The ADC module can operate during Sleep mode if the ADC clock source is active during Sleep mode. The FRC oscillator is a logical choice for operation in Sleep mode. ADC operation during Sleep mode reduces the digital switching noise from the rest of the microcontroller during the conversion process.

If any of the ADC interrupts are enabled, the device will wake from Sleep mode when the ADC interrupt occurs. The program execution will resume at the ADC ISR if the ADC interrupt is greater than the current CPU priority. Otherwise, execution will continue from the instruction after the PWRSAV instruction that placed the device in Sleep mode.

For operation during Sleep mode, the application must use a conversion trigger source that ensures that the A/D conversion will take place in Sleep mode. For example, the external trigger pin option (TRGSRCx[4:0] = 11111) can be used for performing sampling and conversion while the device is in Sleep mode.

Stopping the ADC module in Sleep/Idle is not recommended due to the need to perform a calibration cycle afterward (5000 cycle). The recommended method to reduce power is to put the module in Standby mode which only requires 200 clocks to re-enter operation. Another alternative method is to disable the module (ADCON=0) and then re-enable the module when SLEEP is exited (which requires a recalibration).