20.5.3.2 Host Clock Synchronization

In a multi-host system, different hosts can have different baud rates. The clock synchronization ensures that when these hosts are attempting to arbitrate the bus, their clocks will be coordinated.

The clock synchronization occurs when the host deasserts the SCLx pin (SCLx intended to float high). When the SCLx pin is released, the BRG is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the BRG is reloaded with the contents of I2CxHBRG[23:0] and I2CxLBRG[23:0] begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device, as illustrated in Figure 20-20.